Verilog HDL 83优先编码器代码（附仿真tb代码）

module encoder83( input [7:0]in, input EI, output reg [2:0]bout, output reg EO, output reg GS );

always@(in or EI) if(EI==0) begin bout<=3’b111; EO<=1; GS<=1; end else casex(in) 8’b0?????? : begin bout<=3’b111;EO<=1;GS<=0;end 8’b10????? : begin bout<=3’b110;EO<=1;GS<=0;end 8’b110???? : begin bout<=3’b101;EO<=1;GS<=0;end 8’b1110??? : begin bout<=3’b100;EO<=1;GS<=0;end 8’b1111_0??? : begin bout<=3’b011;EO<=1;GS<=0;end 8’b1111_10?? : begin bout<=3’b010;EO<=1;GS<=0;end 8’b1111_110? : begin bout<=3’b001;EO<=1;GS<=0;end 8’b1111_1110 : begin bout<=3’b000;EO<=1;GS<=0;end 8’b1111_1111 : begin bout<=3’b111;EO<=0;GS<=1;end endcase

endmodule

仿真tb代码 module encoder83;

// Inputs reg [7:0] in; reg EI; // Outputs wire [2:0] bout; wire EO; wire GS; // Instantiate the Unit Under Test (UUT) encoder83 uut ( .in(in), .EI(EI), .bout(bout), .EO(EO), .GS(GS) ); initial begin // Initialize Inputs in = 0; EI = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here in=8'b0011_1111; EI=1'b1; #100; in=8'b1011_1001; #100; in=8'b1101_1001; end

endmodule