参考资料:Cyclone V Device Handbook (p14 Guideline: Using LVDS Differential Channels)
报错信息:
// Error (129036): Output port TXOUT on atom "LvdsSwitch:LvdsSwitch_inst|LvdsTxFrame:LvdsTxFrame_inst|LVDS_TX_IP:LVDS_TX_IP_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_IP_lvds_tx:auto_generated|lvds_outclk_tx_serialiser", which is a cyclonev_ir_fifo_userdes primitive, is not connected to a valid destination // Info (129050): "TXOUT" port has a maximum fan-out node restriction of 1 destinations, which may have exceeded the value specified as the maximum number of fan-out allowed from the node // Info (129025): Output port TXOUT of atom "LvdsSwitch:LvdsSwitch_inst|LvdsTxFrame:LvdsTxFrame_inst|LVDS_TX_IP:LVDS_TX_IP_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_IP_lvds_tx:auto_generated|lvds_outclk_tx_serialiser" is driving the I input port of atom "o_lvds_tx_clk~output", which is a cyclonev_io_obuf primitive // Info (129025): Output port TXOUT of atom "LvdsSwitch:LvdsSwitch_inst|LvdsTxFrame:LvdsTxFrame_inst|LVDS_TX_IP:LVDS_TX_IP_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_IP_lvds_tx:auto_generated|lvds_outclk_tx_serialiser" is driving the D input port of atom "sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[8]", which is a cyclonev_ff primitive // Info (129025): Output port TXOUT of atom "LvdsSwitch:LvdsSwitch_inst|LvdsTxFrame:LvdsTxFrame_inst|LVDS_TX_IP:LVDS_TX_IP_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_IP_lvds_tx:auto_generated|lvds_outclk_tx_serialiser" is driving the D input port of atom "sld_signaltap:auto_signaltap_0|acq_data_in_reg[8]", which is a cyclonev_ff primitive // Info (129038): Input port I of a cyclonev_io_obuf primitive is a valid destination for output port TXOUT on atom "LvdsSwitch:LvdsSwitch_inst|LvdsTxFrame:LvdsTxFrame_inst|LVDS_TX_IP:LVDS_TX_IP_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_IP_lvds_tx:auto_generated|lvds_outclk_tx_serialiser" // Info (129038): Input port I of a cyclonev_pseudo_diff_out primitive is a valid destination for output port TXOUT on atom "LvdsSwitch:LvdsSwitch_inst|LvdsTxFrame:LvdsTxFrame_inst|LVDS_TX_IP:LVDS_TX_IP_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_IP_lvds_tx:auto_generated|lvds_outclk_tx_serialiser"//----20191125更新
报错信息:Info (129050): "TXOUT" port has a maximum fan-out node restriction of 1 destinations, which may have exceeded the value specified as the maximum number of fan-out allowed from the node
应该是跟扇出系数有关,目前测试得出的结论是:
1. SignalTap不能抓取LVDS TX IP核直接输出的信号。
2. LVDS 接收发送的IP核尽量例化在工程的顶层。
3. LVDS RX IP的输入差分时钟信号只能分配到同一侧的专用时钟输入管教上
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工程文件结构如下图:
从 LVDS TX IP 核例化到共层的顶层,经过了三层“包装”,所以在 Quartus II 编译的时候产生了错误。
具体原因还不清楚,还是在俊龙科技的 FAE 帮助下,才解决问题。
解决方案就是,直接将 Altera Lvds Tx IP 核的例化放到顶层。